[1]刘子浩,赖嘉伟,查宇恒,等.基于ZYNQ的神经网络硬件加速器设计[J].计算机技术与发展,2025,(10):10-17.[doi:10.20165/j.cnki.ISSN1673-629X.2025.0146]
　LIU Zi-hao,LAI Jia-wei,ZHA Yu-heng,et al.Neural Network Hardware Accelerator Design Based on ZYNQ[J].,2025,(10):10-17.[doi:10.20165/j.cnki.ISSN1673-629X.2025.0146]
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基于ZYNQ的神经网络硬件加速器设计()

《计算机技术与发展》[ISSN:1006-6977/CN:61-1281/TN]

卷:
期数:
2025年10期
页码:
10-17
栏目:
嵌入式计算
出版日期:
2025-10-10

文章信息/Info

Title:
Neural Network Hardware Accelerator Design Based on ZYNQ
文章编号:
1673-629X(2025)10-0010-08
作者:
刘子浩1; 赖嘉伟1; 查宇恒1; 唐珂1; 徐荣青1; 孙科学1; 2*
1. 南京邮电大学 电子与光学工程学院、柔性电子(未来技术)学院,江苏南京 210023;
2. 射频集成与微组装技术国家地方联合工程实验室,江苏南京 210023
Author(s):
LIU Zi-hao1; LAI Jia-wei1; ZHA Yu-heng1; TANG Ke1; XU Rong-qing1; SUN Ke-xue1; 2*
1. School of Electronic and Optical Engineering & School of Flexible Electronics (Future Technology),Nanjing University of Posts and Telecommunications,Nanjing 210023,China;
2. Nation-local Joint Project Engineering Lab of RF Integration & Micropackage,Nanjing 210023,China
关键词:
ZYNQ; 神经网络; 硬件加速器; ARM; 现场可编程门阵列
Keywords:
ZYNQ; neural network; hardware accelerator; ARM; field-programmable gate array (FPGA)
分类号:
TP391.4
DOI:
10.20165/j.cnki.ISSN1673-629X.2025.0146
摘要:
针对传统神经网络加速器功耗较高的问题,提出了一种基于ZYNQ芯片的硬件加速器。该加速器针对所部署的YOLOv3-tiny算法的特性采用软硬件协同工作的方法,将算法在ZYNQ异构平台上进行拆分。ZYNQ的PS端负责适合于CPU串行调度的任务,PL端负责复杂的并行计算,充分发挥各自优势。同时对乘法器和加法器的使用进行优化,用一个DSP实现两个8比特乘法运算,并采用三叉树的加法器结构代替二叉树,使系统的资源消耗和时序得到了进一步优化。完成电路各个模块的设计后对系统进行级联,在ZYNQ平台上进行系统测试。实验结果表明,该系统仅仅使用了18.15%的BRAM资源和14.65%的DSP资源,功耗仅为2.144W,同时能效比达到了12.66,对比GPU和CPU平台有显著提升。证明该系统可以在低功耗下实现高性能的目标检测,非常适合于部署到嵌入式移动端。
Abstract:
To solve the problem of high power consumption of traditional neural network accelerators,a hardware accelerator based on ZYNQ chip is proposed. According to the characteristics of the deployed YOLOv3-tiny algorithm,the accelerator uses a hardware and software collaboration method to split the algorithm on the ZYNQ heterogeneous platform. The PS side of ZYNQ is responsible for tasks suitable for serial CPU scheduling,and the PL side is responsible for complex parallel computing,taking full advantage of each other. At the same time,the use of multiplier and adder is optimized,two 8-bit multiplication operations are realized with one DSP,and the adder structure of trinomial tree is used instead of binary tree,so that the resource consumption and timing of the system are further optimized.After completing the design of each circuit module, the system was concatenated,and the system was tested on ZYNQ platform. The ex-perimental results showed that the system only used 18.15% BRAM resources and 14.65% DSP resources,the power consumption was only 2.144W,and the energy efficiency ratio reached 12.66,which was significantly improved compared with the GPU and CPU platforms. It is proved that the system can achieve high performance target detection under low power consumption and is very suitable for deployment to embedded mobile terminal.

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更新日期/Last Update: 2025-10-10